This invention relates to buffer circuits, and more particularly to clocked input buffer circuits used in memories.
Input buffer circuits for memories have been clocked primarily for the purpose of reducing power consumption. A chip select signal CS is provided to indicate when a particular memory chip is to be selected. When the chip is not selected, the memory is powered down to reduce power consumption in the standby mode. When the memory is in use, it is either in a read mode or a write mode as indicated by a write enable signal WE. It is also desirable to minimize power consumption in these modes. In the read mode the input data circuitry for the write mode is not being used so that it can be powered down. Even so there is still power being consumed by the write circuitry, in particular for MOS static random access memories (SRAMs), because of the nature of the data bus driver of the write circuitry. The data bus to be driven is for both input data in the write mode and output data in the read mode. Consequently the data bus driver for the input data must be a tri-state driver to provide a high impedance in the read mode. The data bus driver in use is a pair of insulated gate field effect transistors (IGFETs) in a push-pull arrangement. In the read mode the gates of both transistors are typically held low to provide the tri-state condition.
The bus driver itself does not cause a current drain in the read mode, but there is amplifying circuitry which does. A data input signal received on an external pin of the chip is amplified in several stages and separated into true and complementary signals. Current is drawn from the amplification stage in the read mode because both the true and complementary signals are clamped low. Natural transistors with a zero threshold voltage have been interposed between the output load device of an amplifier and the power supply to interrupt the current path in response to the write enable signal. Only a natural device can be used, otherwise there is an additional voltage drop before the signals reach the push-pull pair which cannot be tolerated. Natural devices are not always available for the design of the chip. It may be desirable to avoid the additional process complexity required to provide natural transistors in addition to depletion and enhancement transistors.
Of course in CMOS technology steady state current flow is easily avoided. For a chip where only N channel transistors are available, the considerations are substantially different than those for CMOS. U.S. Pat. No. 4,103,183, Rosenthal et al, discloses a circuit with structural similarities to the present invention but which are only superficially similar because the circuit is CMOS.
Another disadvantage of holding the inputs of the push-pull pair low is that there is some time delay in bringing an input back to a high level. For N channel transistor buffers of this type a high to low transition is faster than a low to high transition. Logic circuitry using the chip select signal CS and the write enable signal WE is required for holding both inputs low. Having such logic for each driver in a byte-wide memory is disadvantageous.